Mark Bohr Quotations

With the number of transistors on some chips exceeding one billion, it is clear that improvements made for individual transistors can multiply into huge benefits for the entire device. Test chips made on Intel's ultra-low power 65nm process technology have shown transistor leakage reduction roughly 1000 times from our standard process. This translates into significant power savings for people who will use devices based on this technology.

With the number of transistors on some chips exceeding 1bn, it is clear that improvements made for individual transistors can multiply into huge benefits for the entire device. Test chips made on Intel's ultra-low power 65nm process technology have shown transistor leakage reduction roughly 1,000 times from our standard processes. This translates into significant power savings for people who will use devices based on this technology.

It does get a little more challenging every time, but we come up with new technology and tricks to keep things going.

We can be much more competitive in those markets.

We are committed to dry lithography for the test chips and manufacturing.

We have a considerable lead over our competitors in the 45-nanometer generation.

This test chip is usually the first significant step we take in developing new logic technologies.

Things have to be faster and lower power, so it's ever-yet more challenging, but we have come up with some new innovations to scale things and keep things on track.

The number of transistors on some chips exceeds one billion, and it is clear that improvements made for individual transistors can multiply into huge benefits for the entire device. Test chips made on Intel's ultra-low power 65nm process technology have shown transistor leakage reduction roughly 1,000 times from our standard process. This translates into significant power savings for people who will use devices based on this technology.

That is the plan for our standard technology. Immersion is still an option that we're looking at for 32-nm.

It will pack about two times as many transistors per unit area and use less power. It will help future products and platforms deliver improved performance.